The ManArray( Embedded Processor Architecture

The BOPS ManArray architecture is presented as a coprocessor platform for the embedded processor domain, consisting of scalable design points. As an array processor, a single architecture definition and tool set supports multiple configurations of processing elements (PEs) from low end single PE to large arrays of PEs. The ManArray selectable parallelism architecture mixes control-oriented operations, practical VLIW, packed data, and distributed array processing in a cohesive independently selectable manner. In addition, scalable conditional execution and single cycle communications across a high connectivity low cost network are integrated in the architecture allowing another level of selectivity that enhances the application of the parallel resources to providing high performance algorithms. Coupled with the array coprocessor is a scalable DMA engine that runs in the background and provides programmer selectable data distribution patterns and a high bandwidth data streaming interface to system peripherals and global memory. This paper introduces the embedded scalable ManArray architecture and selectable parallelism. A number of benchmarks are presented demonstrating the capability of this new architecture. For example, a 2x2 ManArray can process a distributed 256 point complex FFT in 425 cycles and a 8x8 2D IDCT in 34 cycles that meets IEEE standards.